The present invention relates generally to phase lock loops. More particularly, the present invention relates to a method and apparatus for improving the capture and lock characteristics of bi-phase phase lock loops.
A phase lock loop (PLL) is a circuit which effectively locks the phases of an input signal and a reference signal. A conventional PLL can be described as a noninductive, tunable active filter with an adjustable bandwidth. When the phase difference between the reference signal and the input signal is constant, the phase loop is locked. If either the input or reference signal changes phase, a phase detector in the PLL will produce an error signal which is proportional to the magnitude and polarity of the phase change. This error signal effects a change in the phase of the reference signal, so that a lock is established once again. PLLs are used in a wide variety of applications, including FM radio demodulation (as the audio signal is simply the error signal), frequency shift keying (FSK) demodulation, frequency synthesis, data synchronization, signal conditioning, and motor speed controls, among other applications. In the field of generator excitation systems, thyristor bridges are used to control the excitation of the generator, and a phase lock loop can be employed to maintain gate control over the thyristor bridges.
Known PLLs do not provide adequate speed and reliability when the phase input to the PLL is reversed. Where there is a relatively large phase change, existing PLLs do not perform satisfactorily and made have a region of error or "false lock".
The angle between two sinusoidal signals may be described by the arctan of one signal divided by the other. PLL's may use an error signal formed by this mathematics to improve locking characteristics but such methods are computationally complex ,require embellishment and are not sufficiently robust for certain applications.
It would be highly desirable to enhance the lock and capture characteristics and range in a phase lock loop, especially for bi-phase phase lock loops such as those used in connection with generator excitation systems. It would further be desirable to increase the linear range of operation of a PLL beyond the 90 degrees of conventional PLLs. It would further be desirable to achieve improved locking without exceeding the original bandwidth of the PLL.